• 专利附录
  • 专利说明
  • 权利要求
  • 类似技术
  • 同族专利
  • 引用文献
  • 法律状态
  • 优先权
    • 专利摘要:
    The invention relates to an inverter circuit which has an inverter, in particular an inverter half-bridge circuit, with at least two switches connected in series and supplied with direct voltage, at the center of which the switch can be provided with an alternating voltage, and a control unit which does so is set up to clock the switches and to evaluate a measurement signal tapped at the center point, in particular a center point voltage, and to set the timing of each of the switches separately in such a way that a dead time between deactivating one of the switches and activating another switch depending on the measurement signal is set variably.
    公开号:AT16743U1
    申请号:TGM122/2015U
    申请日:2015-05-12
    公开日:2020-07-15
    发明作者:Nesensohn Christian；Wynnyczenko Oliver
    申请人:Tridonic Gmbh & Co Kg；
    IPC主号:
    专利说明:

    description
    INVERTER SWITCHING WITH ADAPTIVE DEAD TIME
    The invention relates to an inverter circuit and in particular an inverter half-bridge circuit and a driver circuit for lamps with such an inverter circuit. In addition, the invention relates to a method for controlling an inverter circuit or switching elements such as switches and / or transistors of an inverter. The illuminant can in particular be one or more LEDs.
    Driver circuits for lamps are known from the prior art and are usually supplied starting from an electrical supply, in particular an AC voltage or a mains voltage. This alternating voltage can be supplied to a rectifier and, in particular, based on this, to a power factor correction circuit (PFC circuit) connected downstream thereof, which provide a direct voltage (DC voltage), which may still have a ripple. This generated DC voltage is then fed to a particularly high-frequency clocked inverter, which generates a high-frequency AC voltage from the DC voltage. The alternating voltage generated is then fed to the illuminant, with other circuit components, such as a rectifier and / or a filter, in particular a ripple filter, connected upstream of the illuminant.
    The inverter and in particular the inverter half-bridge usually have two switches connected in series, which can be designed as power transistors (FET, MOSFET) and are clocked by a control unit. A resonant circuit can preferably be supplied starting from the inverter. A transformer can also be provided, e.g. can be used for transmission over an electrically insulating barrier. This transformer can also be coupled to the resonance circuit.
    When switching the switches of the inverter, care must be taken to avoid so-called “hard switching”. “Hard switching” is understood to mean that during a free-running phase of a current through the half-bridge through the free-wheeling diode (parallel to the Switch and if necessary integrated in this) the other switch is turned on. Otherwise the switch may be damaged.
    The switches of the inverter are each switched on by the control unit for a switch-on period (ton time), the switch-on times of the two switches normally being of the same length. The control takes place, for example, in such a way that a so-called dead time fixed taead ix is provided between the switching off of one switch and the switching on of the other switch in the case of an inverter half bridge, during which neither of the two switches activates, i.e. is switched on.
    Fig. 1a shows an example of a section of a driver circuit with an inverter designed as an inverter half-bridge. The higher potential side of the inverter is supplied with a supply voltage Vpoc or a bus voltage. The supply voltage Voc can e.g. 400V. The half-bridge has two switches Ls, HS, which are controlled by a control unit SE. The higher-potential switch HS is controlled by the control unit SE by a control signal hs, while a lower-potential switch LS is controlled by the control unit SE by a control signal Is. A center point voltage Vmp can then be detected at a center point mp of the inverter half bridge.
    Fig. 1b shows an ideal case of the control of the switch LS, HS of the inverter half-bridge and a corresponding, for example, detected by the control unit SE voltage signal Vmp at the center point mp of the inverter half-bridge. The detection of the center point voltage Vmp takes place in particular in a temporal phase of the clocking
    Switch LS, HS, in which the lower-potential switch LS is open. In particular, only the higher potential switch HS is closed during the voltage detection at the center point mp of the inverter. In Fig. 1b an interleaved or mutual clocking of the switches LS, HS and the center point voltage Vmp is shown schematically, a rectangular drive pulse of the drive signal Is for the switch LS is shown with a solid line, while a rectangular drive pulse of the drive signal hs for the potential-higher switch HS is shown in dashed lines. Also illustrated is the dead time period taead_ # x, which is provided, for example, between the end of the switch-on period of the lower-potential switch LS and the beginning of the switch-on period of the higher potential switch HS.
    In Fig. 1b it is also shown that the voltage Vmp rises after switching off the lower-potential switch LS and drops after switching off the higher-potential switch HS. In particular, it is shown that the center point voltage Vmp drops to zero after activation of the higher-potential switch HS before the lower-potential switch LS is activated. The potential at the center point then corresponds to the zero potential until after activation of the lower-potential switch LS the higher-potential switch HS is activated. This is done by using the time between the blocking of the lower-potential switch LS and the conducting of the higher-potential switch HS to pull the potential at the center point mp to the supply voltage Vpc. The dead time taead fix between blocking the higher-potential switch HS and conducting the lower-potential switch LS is, however, used to pull the center point voltage Vmp to zero or earth. This ensures that the potential difference across the switch is as zero as possible when the respective switch is switched on. Switching losses can thus be avoided and the load, in particular for the switches, is kept low.
    However, the course of the voltage curve Vmp is dependent on the load operated by the driver circuit or the connected lamp. This can result in the fact that when the lower-potential switch LS is switched on, the zero potential has not yet been reached if it is to be switched on. This means that the intended dead time taead fix is not sufficient in this case to pull the center point voltage Vmp to the reference potential ground until the lower-potential switch LS is switched on. This is shown in Fig. 2a. Thus, when the lower-potential switch LS is switched on, a voltage other than zero is present. The potential difference when switching on therefore leads to increased switching losses.
    Conversely, when the higher-potential switch HS is switched on, the potential at the center point mp, i.e. the center point voltage Vmp has not yet reached the level of the supply voltage Vpoc and there is therefore a potential at the center point mp which is not equal to the supply voltage Vpoc. This is illustrated in Fig. 2b. If the higher-potential switch HS is now switched on, higher switching losses also arise here due to the rapid increase in the voltage at the center point mp.
    The above and in Figs. The behavior illustrated in FIGS. 2a and 2b can be observed in particular at low loads, which cause a lower edge steepness of the voltage signal Vmp and thus more slowly rising and falling edges. To ensure voltage-free switching, i.e. To achieve switching at the point in time when the voltage across the switches when switching on is zero, an extension of the dead time taead ix would be necessary.
    However, a different behavior can be observed for large loads. This can lead to a steeper slope of the center point voltage Vmp. This can have the consequence that the center point voltage Vmp has already dropped to zero potential after deactivation of the higher-potential switch HS, and so when the lower-potential switch LS is switched on, the center point voltage Vmp has already risen again, as shown in FIG. 2c . Consequently, the potential present at the center point mp is not the zero potential, which also results in circuit losses.
    On the other hand, when the lower-potential switch LS is deactivated and before the higher-potential switch HS is activated, the phenomenon can be observed that the midpoint voltage Vmp has already risen to the operating voltage Voc and already drops again when the higher-potential switch HS is activated, i.e. is turned on. This is illustrated in Figure 2d. As a result, the potential at the center point of the inverter mp differs from the potential of the operating voltage Voc of the inverter, which in turn leads to switching losses.
    Accordingly, the dead time taeaa ix would have to be shortened at high loads in order to be able to ensure the potential difference of zero when the respective switch is switched on.
    Since switching losses in ballasts should be avoided as much as possible, for example to reduce thermal stress, or to protect the electronic components of the driver circuit (when switching, in particular, power transistors with a potential difference other than zero, these can be damaged), the invention provides a solution that allows the inverter to be switched without potential differences.
    The invention therefore provides an inverter circuit, a driver circuit with such an inverter circuit and a method for operating the inverter circuit according to the independent claims. Further developments of the invention are the subject of the dependent claims.
    In a first aspect, an inverter circuit is provided, comprising an inverter, in particular an inverter half-bridge circuit, with at least two switches connected in series and supplied with DC voltage, at the center of which, with alternating clocking, the switch can be provided with an AC voltage, and a control unit which is set up to clock the switches and to evaluate a measurement signal tapped at the center point, in particular a center point voltage, and to set the timing of each of the switches separately in such a way that a dead time between deactivation of one of the switches and activation of another switch is set variably.
    [0018] The control unit can evaluate the measurement signal tapped at the center point in different time phases of the clocking of the switches.
    [0019] A threshold value can be provided for each of the switches. The control unit can evaluate the tapped measurement signal with respect to the threshold values and, depending on the result of the respective evaluation, activate / deactivate the switch for which the threshold value is defined.
    [0020] The control unit can store the threshold value for each switch and / or evaluate and / or store a signal supplied to it as a threshold value for at least one of the switches.
    [0021] The control unit can detect an edge profile of the measurement signal and activate / deactivate each of the switches depending on the edge profile.
    The control unit can activate / deactivate a switch on a rising edge of the measurement signal and another switch on a falling edge of the measurement signal.
    After reaching a threshold value, the control unit can only activate / deactivate the associated switch after a predetermined period of time.
    [0024] The control unit can set the duration of the activation / deactivation of the switches depending on a target frequency.
    The control unit can recalculate the dead time after each / each mutual activation of the switches.
    [0026] The control unit can measure the measurement signal as a voltage value of the center point in a
    Evaluate the phase in which at least the lower-potential switch is open. The dead time can be varied depending on the detected center point voltage.
    [0028] The control unit can each have a comparator for comparing the measurement signal with the respective threshold value.
    [0029] The control unit can evaluate a signal output by each of the comparators and, depending on this, in particular after the dead time has elapsed, activate the switches by means of control signals.
    The control unit can be an IC, ASIC and / or microcontroller.
    [0031] The inverter can feed a resonance circuit, in particular an LLC resonance circuit.
    In another aspect, a driver circuit with an inverter circuit as described above is provided.
    In yet another aspect, a method for operating an inverter, in particular an inverter half-bridge circuit, with at least two switches connected in series and supplied with DC voltage, at the center of which the switch is provided with an AC voltage, and a control unit , which clocks the switches and evaluates a measurement signal tapped at the center point, in particular a center point voltage, and, depending on the measurement signal, adjusts the clocking of each of the switches separately such that a dead time between deactivating one of the switches and activating another switch is variably defined .
    The invention will now be described with reference to the figures. Show it:
    1a schematically shows an inverter control;
    Fig. 1b schematically control signals for inverter switches and a midpoint voltage curve;
    Figs. 2a-2d midpoint voltage curves with different loads;
    3 schematically shows a driver circuit with an inverter switch
    device according to the invention; Figs. 4a and 49 schematically show components of a control unit according to the invention; 5 schematically shows a switch control according to the invention; and
    6 schematically shows an inverter circuit according to an embodiment of the invention.
    Fig. 3 shows a driver circuit 1 with an inverter circuit 6 according to the invention. 3 schematically shows the structure of the driver circuit 1 for operating a lamp 2, in particular an LED section with at least one LED. The LEDs of the LED line can be arranged in series, in parallel or in a series / parallel connection.
    The driver circuit 1 is preferably driven by an input voltage Vin e.g. fed in the form of an alternating voltage or starting from the mains voltage. The input voltage Vin is preferably fed to a rectifier 3 and / or a filter (for example an EMII filter 4 (electromagnetic interference filter) on the input side of the driver circuit 1, which filters out electromagnetic interference.
    The rectified and, if necessary, filtered input voltage of the driver circuit 1 is then preferably fed to a power factor correction circuit (PFC) 5, which generates a supply voltage Vpc, in particular a bus voltage, on the output side. The supply voltage Vpce is preferably a DC voltage or an approximately constant bus voltage, which may have a ripple. E.g. the supply voltage Voc can be a direct voltage (DC voltage) of 400V.
    Alternatively, the supply voltage Voc can also be a DC voltage or a constant voltage such as be a battery voltage. In this case, the rectifier 3, the optional filter 4 and / or the power factor correction circuit 5 can be dispensed with.
    The supply voltage Voc supplies an inverter circuit 6. The inverter circuit 6 is preferably a DC / AC converter which inverts the supply voltage Vpoc by means of an inverter and in particular by means of a half-bridge inverter. The inverter circuit 6 preferably also comprises a resonance circuit (LLC resonance circuit) which is fed by the inverter. An inductance of the resonance circuit can serve as a primary winding for a transformer. The transformer is provided in order to transmit current via a galvanic barrier 7 from a primary side of the transformer to a secondary side of the transformer. The inverter circuit 6 is thus a clocked converter, in which the resonant circuit is fed from the inverter with the at least two switches LS, HS.
    On the secondary side of the galvanically isolating barrier 7, an AC / DC converter 8 is shown, which can also include other components such as a rectifier or a filter. The switches LS, HS are controlled by a control unit 9, which accordingly switches the switches preferably alternately, i.e. in their conductive state, or off, i.e. in their non-conductive state. The secondary side of the U-transmitter supplies a load and / or the illuminant 2.
    The galvanic barrier 7 can be a SELV barrier (safety extra-low voltage barrier) and can be overcome by the transformer, the transformer being able to be designed in particular as a transformer. The transmission of electrical energy from the primary side to the secondary side of the transmitter via the galvanic barrier 7 is likewise controlled or regulated by the control unit 9 by activating the switches LS, HS.
    The control unit 9 is preferably arranged on the primary side of the galvanic barrier 7, but can also be arranged on the secondary side. To set a desired current through the illuminant 2, the control unit 9 then measures an electrical variable on the primary side (double arrow) and / or on the secondary side (double arrow dotted). On the basis of these returned values, the control unit 9 then controls the inverter or the switches of the inverter of the inverter circuit 6 in such a way that the desired current flows through the lamp. The control unit ensures that the load in the form of a light source, in particular in the form of an LED section, is supplied with the desired current.
    The essence of the invention is to increase the load ranges for which the driver circuit can be used and in particular to avoid the problem that the fixed dead time ta4ead fix ZU short for small loads and the dead time taead fix ZU too long for large loads is. The invention therefore provides to provide a threshold value for each switch of the inverter of the inverter circuit 6 and in particular for each of the two switches LS, HS of the half bridge. Whenever the center point voltage Vmp falls below or exceeds the associated threshold value, the associated switch is triggered. The threshold values are thus ideally matched to the voltage conditions at the respective switch. This results in a variable or an adaptive dead time tqead_adpt depending on the flanks of the voltage change at the center point mp of the inverter. This adaptive adaptation of the dead time tgead_adpı IM normal operation of the inverter circuit is present and not, for example, in an error state, the dead time tdead_adpt being specifically changed to prevent damage to the circuit, for the rest, i.e. in normal operation, but is constant.
    4a shows an example of an embodiment of the control unit 9 according to the invention for controlling the inverter of the inverter circuit 6 and in particular the higher-potential switch HS or the lower-potential switch LS. In particular, the
    Control unit 9 is configured in such a way that it can detect the center point voltage Vmp on a voltage divider and, depending on it, can control the switches LS, HS of the inverter by the control signals hs and Is.
    For this purpose, a threshold value can be stored in the control unit 9 for each of the switches, or this threshold value can be supplied to the control unit 9 externally or can be evaluated by the latter. In particular, the control unit 9 can receive or evaluate information about the connected illuminant or the operated load, in particular via a bus, such as a building services bus (e.g. via DALI protocol). It may also be possible that the threshold value can be supplied to each switch of the control unit, for example via the bus, and thus e.g. is adjustable depending on the connected illuminant.
    4b shows in more detail how the control unit 9 can be designed. The center point voltage Vmp or a parameter reflecting it is detected at an input 40 of the control unit 9 and fed to a comparator K1, K2 for each switch. In the example shown, a first comparator K1 is provided for the higher-potential switch HS and a second comparator K2 for the lower-potential switch LS. A threshold value provided for the respective switch is then supplied to each of the comparators K1, K2. A threshold value SWis is e.g. fed to the comparator K1 for the higher-potential switch HS, while a further threshold value SWi_s is fed to the comparator K2 for the lower-potential switch HS. The outputs of the comparators K1, K2, which are based on a comparison of the center point voltage Vmp with the respective threshold value SWus, SWis, are fed to a detection circuit 41, which can also be known as a standard dead time tJead default. The detection circuit 41 can be designed as part of the control unit 9. The control unit 9 then outputs the control signals hs and Is to the switches HS and LS via a respective output 42, 43 in order to control them, in particular to switch them on, depending on the respective comparison of the threshold value for each switch with the center point voltage Vmp, i.e. for their respective switch-on time (ton time).
    It should be noted that it can also be evaluated in each case what the edge profile of the center point voltage Vmp is at the time of comparison. This is shown in FIG. 5. Here the center point voltage curve Vmp is shown and the threshold values SWLis, SWus for the switches LS, HS of the inverter are also plotted. The threshold value SWps represents the threshold value for the higher potential switch HS, while the threshold value SWHs represents the threshold value for the lower potential switch LS.
    As can be seen from the second curve from above, when the threshold value SWus is exceeded on a rising edge of the center point voltage Vmp, a signal is generated by the comparator K1, which indicates that the associated higher-potential switch HS can now be switched on. Likewise, if the threshold value SWis is undershot, the comparator K2 signals that the lower-potential switch LS can now be activated on a falling edge of the center-point voltage Vmpe. The signals from the comparators K1, K2 are only illustrated by way of example and can show other courses. If reaching a threshold value SW_s / SW4s is signaled, a delay time period tyead_adpt begins from the time of the signaling, which is stored in the control unit 9, which can be supplied, or was calculated by it. The delay period taead_adpt can in particular be equal to the period taead_defautt.
    In particular, the delay period tqaelay_defaut is programmable, i.e. changeable during the operation of the control unit 9. Accordingly, the switch-on times of the switches are the result of the target frequency, which is set by the inverter during frequency control. In this respect, the respective dead time taead adpt Aadaptiv by the control unit for each switching cycle, i.e. the switches HS, LS are calculated for each mutual switch-on.
    As shown in FIG. 6, the inverter according to the invention in particular feeds an LLC converter, which is described in more detail below. 6 shows an embodiment of the inverter circuit 6 for supplying the illuminant 2, shown here as an LED.
    6 shows an exemplary embodiment of the AC / DC converter 8 from FIG. 3 and a filter 20 connected downstream thereof. As shown in FIG. 3, the supply voltage Voc supplies the inverter circuit 6 of the driver circuit 1. The input side is in the Inverter circuit 6 a clocked inverter is provided. An inverter in the form of a half-bridge circuit 21 is shown in FIG. 6, for example. The half-bridge circuit 21 is supplied by the supply voltage Vpc and preferably has the lower-potential switch LS and the higher-potential switch HS. It should be understood that the clocked circuit has at least one switch. A flyback converter, for example, can be used as an inverter with a switch.
    The switches LS, HS of the half-bridge circuit 21 can be used as transistors, e.g. FET or MOSFET. The switches LS, HS can be controlled by control signals Is, hs, which are output by the control unit 9. The lower-potential switch LS is connected to a primary-side ground. In contrast, the input voltage VDC is present at the higher potential switch HS of the half-bridge circuit 21.
    At the midpoint mp of the half-bridge circuit 21, i.e. between the two switches LS, HS, the resonance circuit 22 is connected in the form of a series resonance circuit, consisting of a resonance capacitor Cr and a resonance inductance Lr. In addition, a winding L1 is provided in the resonance circuit. Alternatively, according to the invention, a parallel resonance circuit can also be connected at the center point mp of the half-bridge circuit 21. The resonant circuit 22 is provided between the primary-side mass and the center point mp of the half-bridge circuit. The resonance circuit 22 is referred to in this case as an LLC resonance circuit. The resonance capacitor Cr and the resonance inductor Lr preferably form an LC resonance circuit.
    The winding / coil L1 is preferably for the primary winding of a transformer 23 in the form e.g. a transformer. The transformer 23 shown in FIG. 6 comprises the primary winding L1, that is to say the winding L1 of the LLC resonant circuit, and a secondary winding L2 which is electromagnetically coupled to this primary winding L1. Due to the transformer coupling between the winding L1 and the secondary winding L2, energy is transferred across the galvanic barrier 7 if the transformer is controlled accordingly, in particular by controlling the timing of the switches HS, LS by the control unit 9. The transformer 23 can additionally have a leakage inductance and a main inductance (not shown). The leakage inductance can be provided in series with the winding L1. The main inductance can serve to carry the magnetizing current and can preferably be arranged parallel to the winding L1.
    An alternating current (AC current) preferably flows through the secondary winding L2 of the transformer 23 during operation. The voltage of the secondary winding L2 is then preferably fed to a rectifier 24, which in the example shown is formed by the diodes D1 and D2. The secondary winding L2 of the transmitter 23 additionally has a tap or tap, which can be provided in particular as a center tap. This center point tap represents a potential of the rectifier 24 or a potential of the voltage Vie applied to the LED path.
    One side of the secondary winding L2 is connected to an anode of the first diode D1, while the other side of the secondary winding L2 is connected to the anode of the second diode D2. The respective cathodes of the diodes D1, D2 are brought together and form an output potential of the rectifier 24. The rectifier 24 can be coupled on the output side to a storage or filter capacitor C2. In particular, an electrolytic capacitor (ELKO) can be used as the storage capacitor.
    In order to filter a voltage output by the rectifier 24 and in particular to provide a ripple filter, the capacitor C2 is followed by an inductance L £, which in turn is connected to a further capacitor C3. The capacitors C2 and C3 are connected on their higher potential side to the inductor Lf, while they are connected on their lower potential side to the secondary-side ground. The secondary
    side ground potential can differ from the primary side.
    On the primary side of the inverter circuit 6 shown in FIG. 6, means 25 for measuring a current on the primary side or the current through the resonant circuit 22 can be provided. The means 25 for measuring the current Iı_.c through the resonance circuit 22 are preferably designed as a measuring resistor (shunt), which is not shown in FIG. 6. The measuring resistor can be connected in series with the winding L1 of the transformer 23 in a known manner. If an applied voltage is detected by the control unit 9 at the measuring resistor, the control unit 9 is able to detect the current through the resonance circuit 22. Accordingly, the control unit 9 can control the switches LS, HS of the half bridge 21.
    Furthermore, means 26 for measuring a voltage V: via the primary-side winding L1 can be provided on the primary side of the inverter circuit. According to one embodiment, the voltage measurement can be carried out by connecting both sides of the primary winding L1 to the control unit 9 in such a way that the latter can detect the voltage across the inductor L1. Overall, the control unit 9 can therefore have direct information about the voltage Vi: applied to the winding L1. Alternatively, a voltage divider (not shown) can also be provided between the connections of the winding L1 and the control unit 9 can accordingly be supplied with a partial voltage of the voltage divider, which can then reflect a voltage VL1 applied to the winding L1 as an actual signal for the voltage.
    Of course, it can also be provided that the control unit 9 detects a parameter on the secondary side of the circuit shown in FIG. 6 that reflects the current and / or the voltage on the secondary side. The parameter can be fed back, for example, via a resistance or capacitor circuit via the galvanic barrier 7. The control unit 9 can in particular detect a voltage or a current transmitted to the secondary side. Here too, the switches LS, HS of the half-bridge 21 can be controlled accordingly by the control unit 9 (see the indication by the dashed arrow in FIG. 6).
    权利要求:
    Claims (10)
    [1]
    1. Inverter circuit (6), characterized in that the inverter circuit has:
    a. an inverter, in particular an inverter half-bridge circuit (21), with at least two switches (LS, HS) connected in series and supplied with direct voltage (Voc), at their center point (mp) with alternating clocking of the switches (LS, HS) an alternating voltage is available, and
    b. a control unit (9) which is set up to clock the switches (LS, HS) and to evaluate a measurement signal tapped at the center point, in particular a center point voltage (Vme), and the timing of each of the switches (LS, HS) separately so that a dead time (taeaa) between deactivating one of the switches and activating another switch is variably defined.
    [2]
    2, inverter circuit (6) according to claim 1, characterized in that the control unit (9) is set up to evaluate the measured signal tapped at the center point (mp) in different temporal phases of the timing of the switches (LS, HS).
    [3]
    3. inverter circuit (6) according to claim 1 or 2,
    characterized,
    that a threshold value (SWis, SWus) is provided for each of the switches (LS, HS), and the control unit (9) is set up to evaluate the tapped measurement signal with respect to the threshold values (SWis, SWHs), and depending on the result of the activate / deactivate the relevant evaluation (LS / HS) for which the threshold value (SW_s / SW4Hs) is defined; and / or that the control unit (9) is set up to store the threshold value (SWis, SWus) for each switch (LS, HS) and / or in each case a signal supplied to it as a threshold value (SWis, SWhs) for at least one of the switches (LS, HS) to save.
    [4]
    4. Inverter circuit (6) according to one of the preceding claims, characterized in that the control unit (9) is set up to detect an edge profile of the measurement signal and to activate / deactivate each switch (LS, HS) depending on the edge profile; and / or that the control unit (9) is set up to activate / deactivate a switch on a rising edge of the measurement signal and another switch on a falling edge of the measurement signal.
    [5]
    5. Inverter circuit (6) according to one of the preceding claims, characterized in that the control unit (9) is set up, after reaching a threshold value (SWis, SWus), only after a predetermined time period (taeaa) the associated switch (LS, HS) to activate / deactivate; and / or that the control unit (9) is set up to set the duration of the activation / deactivation of the switches (LS, HS) depending on a target frequency.
    [6]
    6. Inverter circuit (6) according to one of the preceding claims, characterized in that the control unit (9) is set up to recalculate the dead time (taeaa) after each / each mutual activation of the switches (LS, HS); and / or that the dead time (taeaa) can be varied depending on the detected center point voltage (Vmp).
    [7]
    7. Inverter circuit (6) according to one of the preceding claims, characterized in that the control unit (9) is set up to evaluate the measurement signal as a voltage value of the center point (mp) in a phase in which at least the lower-potential switch (LS) is open.
    [8]
    8. Inverter circuit (6) according to one of the preceding claims, characterized in that the control unit (9) each have a comparator (K1 / K2) for comparing the
    Has measurement signal with the respective threshold (SWis / SWus);
    and or
    that the control unit (9) is set up to evaluate a signal output by each of the comparators (K1, K2) and, depending on this, in particular after the dead time (taeaa), the switches (LS, HS) by means of control signals (Is, hs) to activate.
    [9]
    9. Driver circuit (1), characterized in that the driver circuit with an inverter circuit (6) according to one of claims 1-8 is provided.
    [10]
    10. Method for operating an inverter circuit (6) with an inverter, in particular an inverter half-bridge circuit, characterized in that the inverter has:
    a. at least two switches (LS, HS) connected in series and supplied with direct voltage (VDC), at the center point (mp) of which an alternating voltage is provided with mutual switching of the switches (LS, HS), and
    b. a control unit (9) which clocks the switches (LS, HS) and evaluates a measurement signal tapped at the center point, in particular a center point voltage (Vmp), and, depending on the measurement signal, separately adjusts the clocking of each of the switches (LS, HS) in this way that a dead time (taeaa) is variably set between deactivating one of the switches and activating another switch.
    5 sheets of drawings
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    同族专利:
    公开号 | 公开日
    WO2016087206A1|2016-06-09|
    DE102014224752A1|2016-06-09|
    引用文献:
    公开号 | 申请日 | 公开日 | 申请人 | 专利标题
    US20100156366A1|2005-06-21|2010-06-24|Rohm Co., Ltd.|Step-down switching regulator, control circuit thereof, and electronic device using the same|
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    JP2009290812A|2008-06-02|2009-12-10|Internatl Rectifier Corp|Dead time control circuit|
    DE102012111905A1|2011-12-07|2013-06-13|Maxim Integrated Products, Inc.|Direct current -DC converter has delay module to delay edges of second signal among two signals based on determined time differences between edges of two signals|
    DE102004009994A1|2004-03-01|2005-09-22|Tridonicatco Gmbh & Co. Kg|Overcurrent and mid point voltage detection|
    JP6069958B2|2012-08-27|2017-02-01|富士電機株式会社|Switching power supply|FR3064847B1|2017-04-04|2019-12-27|Valeo Siemens Eautomotive France Sas|METHOD FOR MANAGING THE SWITCHES OF A FREQUENCY-CONTROLLED SWITCH ARM|
    FR3084221B1|2018-07-17|2021-02-26|Valeo Siemens Eautomotive France Sas|PROCESS FOR MANAGING THE SWITCHES OF A FREQUENCY CONTROL SWITCH ARM|
    法律状态:
    2022-01-15| MM01| Lapse because of not paying annual fees|Effective date: 20210531 |
    优先权:
    申请号 | 申请日 | 专利标题
    DE102014224752.7A|DE102014224752A1|2014-12-03|2014-12-03|Inverter circuit with adaptive dead time|
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